Drimva

Intel

Design Verification Engineer

$106K–$149K

US, California, Santa Clara · Full-time · Posted Sep 11, 2026

Experience
3+ months of internship experience in a hardware design or verification environment.
Education
BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
Visa sponsorship
Not eligible for Intel immigration sponsorship.

About the job

Verifies next-generation interconnect and chassis IP by developing testbenches and tests, debugging simulation failures, and contributing to functional coverage and regression analysis.

What you'll do

  • Develop testbench components, constrained-random stimulus, and functional checkers; run and debug simulations and root-cause failures.
  • Contribute to functional coverage plans, coverage closure, and regression triage.
  • Use AI-assisted coding and debugging tools and contribute automation and scripting.

What they ask for

  • BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
  • At least 3 months of internship experience in a hardware design or verification environment.
  • Foundation in logic design and digital circuits; ability to read and reason about RTL; demonstrated algorithmic thinking and software fundamentals.
  • Proficiency in at least one of C/C++, Python, or SystemVerilog; coursework or project exposure to two or more listed subject areas; regular use of AI coding assistants in coursework or projects.

Nice to have

  • Coursework or project work in hardware verification, FPGA design, or RTL simulation; exposure to SystemVerilog, UVM concepts, or assertion-based verification.
  • Familiarity with AXI, AHB, or PCIe, or cache/memory hierarchy concepts; Linux, git, or build/test automation scripting.

Pay

$105,650.00-149,150.00 USD (annual salary; posting describes this as target compensation, not specifically base salary or total pay).

Tools

C/C++, Python, SystemVerilog, ModelSim, VCS, Questa, UVM, git

AI focus

Use AI-assisted coding and debugging tools regularly as a core development workflow and productivity tool.

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 4, 2026 (UTC)