Drimva

Intel

Director, Process Engineer – Dry Etch

$211K–$298K

US, Oregon, Hillsboro +1 · Director · Full-time · Posted Sep 23, 2026

Location
US, Oregon, Hillsboro
US, Arizona, Phoenix
Experience
10+ years of relevant semiconductor industry experience; also specifies 10+ hands-on experience and 10+ history of collaboration, without stating a separate unit for either.
Education
Master's degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Materials Science, Physics, Chemistry, or a related technical field.

About the job

Leads dry etch process development, transfer, optimization, and sustaining across advanced CMOS technologies, improving manufacturing capability, yield, performance, and cost.

What you'll do

  • Develop, optimize, and sustain dry etch processes; execute experiments and resolve process and equipment issues.
  • Improve process capability, including profile and critical-dimension control, uniformity, selectivity, defectivity, throughput, yield, and cost.
  • Support process transfer and high-volume manufacturing readiness, partnering with factory teams, cross-functional organizations, and equipment suppliers.

What they ask for

  • 10+ years of relevant semiconductor industry experience focused on dry etch development, process integration, or high-volume manufacturing support.
  • Master’s degree in a listed technical field or related technical field.
  • 10+ hands-on experience with dry etch process development, plasma etch equipment, recipe optimization, process characterization, and troubleshooting.
  • Ability to work in a dynamic fab environment, support urgent manufacturing issues, and drive technical closure under schedule pressure.

Nice to have

  • Doctoral degree in a related technical field.
  • Experience with advanced CMOS technologies, such as GAA, advanced patterning, or highly scaled interconnect structures.

Pay

$211,400.00-298,440.00 USD (annual target compensation; base salary or total pay not specified)

Tools

plasma etch, reactive ion etch (RIE), atomic layer etch (ALE), CD-SEM, Gate-All-Around (GAA), statistical process control, design of experiments

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 4, 2026 (UTC)