Drimva

Intel

EDA Tools Software Engineer

$96K–$182K

US, Oregon, Hillsboro · Full-time · Posted Oct 28, 2026

Experience
Bachelor’s route: 6+ months of hands-on domain experience, which may include internships, academic projects, coursework, or hands-on training; Master’s route: no prior professional experience.
Education
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or a Master’s degree in one of these fields.
Visa sponsorship
The posting refers candidates to Intel’s U.S. immigration sponsorship guidelines but does not state a specific visa policy.

About the job

Develops and validates VLSI layouts and tape-in collateral for Intel process technology development, including design-rule verification, tool-flow troubleshooting, and software support.

What you'll do

  • Verify VLSI layout compliance with design rules and provide quality assurance for FRAT designs.
  • Troubleshoot design and PDK verification issues across physical-design flows and tools.
  • Develop and support tape-in collateral, including software code, cell designs, testcases, and verification content.

What they ask for

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus 6+ months of hands-on domain experience; or a Master’s degree in one of these fields with no prior professional experience.
  • Coursework or background in VLSI design or CAD, Python or C++ programming, semiconductor device physics or basic electrical circuit theory, and silicon manufacturing flows.

Nice to have

  • Experience with Cadence Virtuoso, Klayout, Calibre DRV, or Calibre; knowledge of DRC, ICV, or IC Validator.
  • Familiarity with semiconductor processing, VLSI mask layout or verification, UNIX/Linux, or custom design and verification tools.

Pay

$95,640.00-181,940.00 USD (base salary)

Tools

Python, C++, Cadence Virtuoso, Klayout, Calibre DRV, Calibre, IC Validator, UNIX/Linux

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 4, 2026 (UTC)