Drimva

Intel

EMIB-T Substrate Yield Lead

$181K–$255K

US, Arizona, Phoenix · Full-time · Posted Aug 17, 2026

Experience
6+ years with a Master’s degree or 4+ years with a PhD; also requires 5+ years in a relevant industry field.
Education
Master’s degree or PhD in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline.

About the job

Leads EMIB-T substrate yield performance, technology development, and manufacturing readiness, coordinating yield improvement and deployment across Intel teams and suppliers.

What you'll do

  • Own substrate yield performance and drive defect reduction, process optimization, and yield improvement plans.
  • Lead cross-functional reviews, prioritize and close yield and supplier issues, and track program milestones.
  • Develop yield intelligence systems, including dashboards, analytics, computer vision, and AI/ML defect detection.

What they ask for

  • Master’s degree with 6+ years or PhD with 4+ years in a related technical discipline.
  • 5+ years in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field.
  • Hands-on substrate, advanced packaging, or semiconductor yield engineering experience, including statistical analysis, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution.
  • Experience developing or deploying yield monitoring systems, automated analytics, image analytics, computer vision, AI/ML defect detection, or automated defect classification.

Nice to have

  • Experience working directly with substrate suppliers and external manufacturing partners.
  • Experience with advanced packaging technologies such as EMIB, EMIB-T, TSV, 2.5D/3D integration, substrates, or heterogeneous integration.

Pay

$180,770.00-255,200.00 USD (base salary)

Tools

EMIB-T, SPC, DFM/DFY, HVM, TSV, 2.5D/3D integration, computer vision, AI/ML

AI focus

Develop and scale yield intelligence infrastructure, including AI/ML-based defect detection and automated defect classification.

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)