Drimva

Intel

Hardware Engineer

$122K–$232K

US, California, Santa Clara · Full-time · Posted Sep 17, 2026

Experience
Minimum combinations: 4+ years with a Bachelor’s degree, 3+ years with a Master’s degree, or 0 years with a PhD; also 3+ years in specified hardware design areas.
Education
Electrical Engineering or similar STEM field; Bachelor’s, Master’s, or PhD as specified.

About the job

Designs and verifies optical transceiver hardware and evaluation boards, from product requirements and schematic/layout work through bring-up and performance optimization.

What you'll do

  • Own PCBA design execution, including schematic, layout, simulation, design verification, and EVT/DVT activities.
  • Coordinate high-speed signal and power integrity design, collaborate across engineering and supply-chain teams, and resolve board or transceiver issues.
  • Maintain design documentation, lead design reviews, and communicate risks and mitigation plans.

What they ask for

  • Bachelor’s degree plus 4+ years, Master’s degree plus 3+ years, or PhD plus 0 years in Electrical Engineering or a similar STEM field.
  • 3+ years in hardware/circuit design, schematic design, and layout floor planning.
  • Experience with Cadence tools and high-density, high-speed multilayer board design.
  • Experience selecting and optimizing voltage regulators, uControllers, and DAC/ADCs; PCB/product bring-up and laboratory optical and electrical measurements; and high-speed Tline design and layout guidelines.

Nice to have

  • Experience with high-volume PCB/substrate fab houses, PCB stackup selection, electronics CAD/modeling, and PI/SI simulations.
  • Knowledge of transceiver and test-board design principles, optical-module protocols, and high-speed characterization using AWG, DCAM, VNA/LCA.

Pay

$122,440.00-232,190.00 USD (target compensation; base salary or total pay not specified)

Tools

Cadence, SPI, I2C, MDIO, CMIS, AWG, DCAM, VNA/LCA

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 4, 2026 (UTC)