Drimva

Intel

Module Engineer On Shift (MEOS)

$85K–$162K

US, Arizona, Phoenix · Full-time · Posted Oct 15, 2026

Experience
2+ years of hands-on experience in assembly and packaging technologies or technology manufacturing; experience may be obtained through education, projects, research, jobs, or internships.
Education
Bachelor’s degree in mechanical engineering, materials science engineering, chemical engineering, electrical engineering, applied technology or a related field.
Visa sponsorship
Not eligible for Intel immigration sponsorship.

About the job

Develops and optimizes semiconductor assembly and packaging processes, equipment, and reliability practices for next-generation products in an on-site manufacturing role.

What you'll do

  • Design, test, and optimize packaging processes and equipment to meet quality, reliability, yield, cost, and manufacturability goals.
  • Apply SPC and DOE, conduct simulated-field tests, and develop techniques to detect packaging quality and reliability issues.
  • Manage packaging process lifecycle and collaborate with suppliers, procurement, and internal stakeholders on specifications and improvements.

What they ask for

  • Bachelor’s degree in mechanical engineering, materials science engineering, chemical engineering, electrical engineering, applied technology or a related field.
  • 2+ years of hands-on experience in assembly and packaging technologies or technology manufacturing.

Nice to have

  • 2+ years of experience with SPC and DOE; laser, optical systems, or semiconductor assembly processes; or semiconductor packaging/manufacturing.
  • Experience with equipment adjustment, process characterization, manufacturability, or data tools such as Python, JMP, or Minitab.

Pay

$85,200.00-162,500.00 USD (target compensation; whether base salary or total pay is not specified)

Tools

Statistical Process Control (SPC), Design of Experiments (DOE), Python, JMP, Minitab

Model-written summary · the original posting is authoritative

First seen Oct 16, 2026 · Last verified Nov 4, 2026 (UTC)