Drimva

Intel

Module Engineering PhD Intern

$121K–$121K

US, Oregon, Hillsboro · Internship · Posted Sep 10, 2026

Experience
3+ months of hands-on experience; research, laboratory work, internships, academic projects, or industry experience are stated alternatives.
Education
Currently pursuing a PhD degree in a listed or related STEM discipline.

About the job

Supports the development and optimization of semiconductor manufacturing processes and equipment to improve performance, reliability, and yield.

What you'll do

  • Develop, optimize, and implement manufacturing processes for semiconductor production modules.
  • Troubleshoot, sustain, and qualify manufacturing equipment and analyze process and equipment data to identify improvements.
  • Collaborate with engineering teams on process control methodologies and technical projects focused on equipment performance, process optimization, and yield.

What they ask for

  • Currently pursuing a PhD in Engineering, Materials Science, Physics, Chemistry, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related STEM discipline.
  • At least 3 months of hands-on experience through research, laboratory work, internships, academic projects, or industry experience.
  • Fundamental understanding of semiconductor manufacturing processes, process engineering, or advanced manufacturing methodologies.
  • Strong analytical, problem-solving, and technical communication skills.

Nice to have

  • Research experience in semiconductor fabrication, process development, materials engineering, or manufacturing technologies; experience with process characterization, statistical analysis, data analytics, or experimental design.
  • GPA of 3.0 or higher; knowledge of semiconductor manufacturing equipment, process control systems, and equipment qualification techniques.

Pay

$120,898.00-120,902.00 USD (annual target compensation; base salary or total pay not specified)

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 4, 2026 (UTC)