Drimva

Intel

Neuromorphic Front-End Silicon Lead

$221K–$312K

US, Oregon, Hillsboro +4 · Full-time · Posted Sep 3, 2026

Location
US, Oregon, Hillsboro
US, California, Folsom
US, California, Santa Clara
US, Texas, Austin
US, Arizona, Phoenix
Experience
10+ years hands-on design; 5+ years RTL design and modern ASIC flows; 3+ years leading silicon design and/or verification teams.
Education
MS in Electrical/Computer Engineering, Computer Science, or a related field.

About the job

Leads front-end silicon design and verification for neuromorphic chiplets and IP, from microarchitecture through post-silicon validation.

What you'll do

  • Translate hardware innovations into implementable microarchitectures and lead design, verification, and post-silicon validation.
  • Evaluate and integrate IP, collaborate on custom circuits and physical design, and coordinate with software and systems teams for enablement and bring-up.
  • Mentor engineers and improve design and verification practices.

What they ask for

  • MS in Electrical/Computer Engineering, Computer Science, or a related field.
  • 10+ years of hands-on design experience in processors, accelerators, SoCs, or custom ASICs.
  • 5+ years of RTL design experience (Verilog/SystemVerilog) and modern ASIC flows.
  • 3+ years leading silicon design and/or verification teams.

Nice to have

  • PhD with a research background in hardware acceleration, especially AI.
  • Experience with advanced packaging and heterogeneous integration, asynchronous design, custom memory/circuit co-design, emulation or FPGA prototyping, low-power methods, security features, or multiple product tape-outs.

Pay

$220,920.00-311,890.00 USD (target compensation; base salary or total pay not specified)

Tools

Verilog, SystemVerilog, Ethernet, PCIe, UCIe, UPF, Root of Trust, secure boot

AI focus

Leads silicon development for neuromorphic chiplets and IP, translating neuromorphic and AI accelerator concepts into hardware.

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)