Intel
Platform Integration Engineer
$164K–$232K
US, California, Santa Clara · Full-time · Posted Oct 21, 2026
- Experience
- 6+ years with a bachelor's degree, or 4+ years with a master's degree, in RTL design and SystemVerilog.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field; or a master's degree in a relevant field.
About the job
Designs and integrates RTL IP blocks and subsystems for full-chip designs, optimizing power, performance, area, and timing while supporting validation and IP-to-SoC handoff.
What you'll do
- Develop RTL logic designs and simulations, and define architecture and microarchitecture features.
- Optimize designs against power, performance, area, and timing goals; address verification failures and physical design constraints.
- Drive quality assurance compliance and collaborate across teams to enable IP-to-SoC integration.
What they ask for
- Bachelor's degree in a relevant STEM field and 6+ years of RTL design and SystemVerilog experience, or a relevant master's degree and 4+ years.
- Experience with front-end design tools for synthesis, static timing analysis (STA), and lint checks.
- Experience with AMBA and coherent protocols such as IDI or CHI.
- Knowledge of logic design, state machines, and network-on-chip architectures.
Nice to have
- Experience with high-speed interconnect designs and power-performance optimization.
- Python, Perl, or Tcl scripting for automation.
Pay
$164,470.00-232,190.00 USD (target compensation; pay type not specified)
Tools
RTL, SystemVerilog, synthesis, static timing analysis (STA), lint checks, AMBA, IDI, CHI
Model-written summary · the original posting is authoritative