Intel
Pre-Silicon Verification Engineer
$122K–$173K
US, Oregon, Hillsboro +5 · Full-time · Posted Oct 9, 2026
- Location
- US, Oregon, Hillsboro
US, Massachusetts, Beaver Brook
US, California, Folsom
US, California, Santa Clara
US, Texas, Austin
US, Arizona, Phoenix - Experience
- Bachelor's: 4+ years; OR Master's: 3+ years; OR PhD: 1+ years of relevant experience. Also requires 2+ years in/with the specified verification methodologies and scripting languages.
- Education
- Bachelor's, Master's, or PhD in Electrical or Computer Engineering or a related field.
About the job
Verifies clock-generator IPs such as PLL and FLL before silicon fabrication, developing tests and environments, debugging issues, and supporting mixed-signal validation.
What you'll do
- Develop System Verilog and UVM test benches, verification environments, and tests for IP validation.
- Verify clock-generator IPs against specifications, maintain verification infrastructure, and debug pre-silicon issues.
- Lead mixed-signal validation activities, document test plans, and collaborate with design teams on IP features.
What they ask for
- Bachelor's in Electrical or Computer Engineering or a related field and 4+ years of relevant experience; OR Master's in one of these fields and 3+ years; OR PhD in one of these fields and 1+ years.
- 2+ years of experience with design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools.
- 2+ years of experience with scripting languages such as Python and Perl.
Nice to have
- Expertise in System Verilog UVM coding and debugging.
- Familiarity with PLL/FLL or SOC clocking and related RTL development.
Pay
$122,440.00-172,860.00 USD (total compensation)
Tools
System Verilog, UVM, Python, Perl, EDA tools, PLL, FLL, RTL
Model-written summary · the original posting is authoritative