Intel
Principal Engineer - Standard Cell Design
$221K–$312K
US, California, Santa Clara +4 · Principal · Full-time · Posted Jul 14, 2026
- Location
- US, California, Santa Clara
US, Oregon, Hillsboro
US, California, Folsom
US, Texas, Austin
US, Arizona, Phoenix - Experience
- 10+ years of industry experience with foundation IP design, design-technology co-optimization & advanced semiconductor technology.
- Education
- Ph.D. or Master's degree.
About the job
Leads standard-cell library strategy and circuit innovation, optimizing PPA and Vmin across advanced process nodes while guiding teams and partnering with Intel foundry customers, product teams, and EDA partners.
What you'll do
- Define standard-cell library strategy and develop scalable circuit methodologies.
- Lead circuit innovation and PPA/Vmin optimization, including sequential and clocking circuits.
- Partner across foundry, product, process, and EDA teams; analyze silicon and design data and mentor engineers.
What they ask for
- Ph.D. or Master's degree.
- 10+ years of industry experience with foundation IP design, design-technology co-optimization & advanced semiconductor technology.
- In-depth understanding of MOSFET characteristics, transistor-level device physics, layout, and variability at advanced technology nodes.
- Experience with standard cell characterization tools and Spice circuit simulations.
Nice to have
- Track record of technical leadership and delivery; experience leading working groups or driving cross-org alignment.
- Background in compact modeling, characterization, or EDA tool interaction; experience across CPU, GPU, or SoC design teams.
Pay
$220,920.00-311,890.00 USD (annual salary; target compensation)
Tools
Spice
Model-written summary · the original posting is authoritative