Product Development/DFX Lead - Neuromorphic Computing

What you'll do

• Architect SoC-level DFT solutions covering synchronous and asynchronous designs, including scan insertion and compression flows.
• Develop scalable tools and flows to generate and validate test vectors pre-silicon.
• Lead silicon power-on, tester-content enablement, failure debugging, and maintenance of test tools and flows.

What they ask for

• Bachelor’s degree and 6+ years, or Master’s degree and 4+ years, of hands-on DFT experience from architecture to silicon bring-up.
• 6+ years architecting the DFT stack, including scan insertion, compression, and ATPG vector generation.
• 4+ years owning IP- and SoC-level scan constructs such as boundary scan (JTAG), TAP, and BIST/MBIST.
• 1 year debugging post-silicon and driving circuit changes for testability and reliability improvements.

Nice to have

• Experience with custom ASICS or AI/ML accelerator design; asynchronous architectures and circuits.
• 1+ year using AI tools for tool-flow setup, debugging, and productivity improvement.

Pay

$141,910.00-269,100.00 USD (total compensation)

Tools

DFT, DFX, DFD, DFM, RTL, System-Verilog, System-C, ATE

AI focus

Preferred experience using AI tools to set up tool flows, debug, and improve productivity; the role supports neuromorphic computing for physical AI systems.