Drimva

Intel

Product Failure Analysis Engineer - SCAN Design for Test

$142K–$269K

US, Oregon, Hillsboro · Full-time · Posted Oct 6, 2026

Experience
6+ years in the stated minimum qualification alternative: bachelor's plus 6+ years, master's plus 4+ years, or PhD plus 2+ years. Posting also describes 6–12 years of semiconductor experience.
Education
Bachelor’s degree in electrical engineering, computer engineering, or a related STEM discipline; OR master's degree; OR PhD.

About the job

Leads silicon failure analysis and scan-based debug for Intel Foundry products, identifying root causes and corrective actions while improving diagnostic methods and automation.

What you'll do

  • Investigate silicon failures using logical diagnosis and physical analysis tools, and determine root causes.
  • Partner across design, test, validation, process, yield, and manufacturing teams to resolve product and process issues.
  • Develop debug tools, methodologies, and automation to improve diagnosis and support design-for-debug.

What they ask for

  • Bachelor’s degree in electrical engineering, computer engineering, or a related STEM discipline with 6+ years of hands-on experience, OR master's degree with 4+ years, OR PhD with 2+ years.
  • Expertise in Design for Test (DFT) tools and techniques, SCAN ATPG methodology, and Scan Chain Diagnosis.
  • Experience with fault isolation, fault modeling, and Scan architecture (SSN).
  • Experience with Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, simulation and diagnosis tools; and developing debug automation using Python, Perl, or TCL.

Nice to have

  • JTAG and validation/debug research methodologies.
  • Experience in foundry, fabless semiconductor, or high-volume manufacturing environments supporting customer product bring-up, yield ramp, or production qualification.

Pay

$141,910.00-269,100.00 USD (target compensation; posting does not specify base salary or total pay)

Tools

DFT, SCAN ATPG, Scan Chain Diagnosis, Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, Python

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)