Intel
Quantum Packaging Signal/Power Integrity (SI/PI) Engineer
$142K–$200K
US, Oregon, Hillsboro · Full-time · Posted Sep 23, 2026
- Experience
- M.S. route: 3+ years of experience. Ph.D. route: academic or work experience in related areas. Preferred: 1+ years with testchip SI software for large-scale automation.
- Education
- M.S. in Electrical Engineering, Physics, or related field; or Ph.D. in Electrical Engineering, Physics, or related field.
About the job
Models and simulates packaging hardware and system-level designs for Intel’s silicon quantum dot technology, working with multidisciplinary teams to meet or develop design requirements.
What you'll do
- Model and simulate packaging hardware, including redistribution layers, IC substrates, and silicon testchip routing.
- Perform end-to-end system-level simulations and collaborate with stakeholders on design requirements and packaging hardware.
- Deliver design milestones and communicate designs through presentations and documentation.
What they ask for
- M.S. in Electrical Engineering, Physics, or a related field and 3+ years of relevant experience; or a Ph.D. in one of those fields with academic or work experience in related areas.
- Experience in SI/PI modeling, simulation, and optimization using software such as SIwave, HFSS, ADS, or related tools.
- Experience with SI/PI/thermal impacts on IC substrate design choices.
- Design experience with large form factor IC substrates.
Nice to have
- 1+ years of experience with testchip SI software for large-scale automation, such as RaptorH/X.
Pay
$141,910.00-200,340.00 USD (target compensation; pay type not specified)
Tools
SIwave, HFSS, ADS, RaptorH/X
Model-written summary · the original posting is authoritative