Qubit Control Physical Design Engineer

What you'll do

• Drive RTL-to-GDS convergence and block-level physical design, including floor planning, timing closure, power and clock distribution, and physical verification.
• Debug timing, EM/IR, LVS, and DRC issues and lead sign-off activities.
• Collaborate with CAD, methodology, and custom IP teams to improve design flows, methodologies, memory macros, and standard cell libraries.

What they ask for

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 6+ years of hands-on physical design experience, or a Master's degree with 4+ years of relevant experience.
• Experience with floor planning, timing constraints definition, synthesis, place-and-route, and achieving product KPIs.
• Proficiency in Python, Perl, and TCL for design-flow automation and debugging; hands-on experience debugging FEV and RV reports and implementing ECOs.
• Strong understanding of chiplet integration and advanced packaging; experience using AI tools to improve workflows, debugging, and productivity.

Nice to have

• Static timing analysis across interfaces such as SerDes and UCIe; experience with Cadence Virtuoso or Synopsys Fusion Compiler.
• Knowledge of asynchronous architectures and circuits, Java or C++ EDA software development, or power-efficient and high-frequency physical design.

Pay

$141,910.00-269,100.00 USD (annual salary; target compensation)

Tools

Python, Perl, TCL, Cadence Virtuoso, Synopsys Fusion Compiler, Java, C++

AI focus

Use AI tools to set up workflows, streamline debugging, and improve productivity.