Intel
Semiconductor Packaging Integration Research Manager
$221K–$312K
US, Arizona, Phoenix +1 · Manager · Full-time · Posted Sep 11, 2026
- Location
- US, Arizona, Phoenix
US, Oregon, Portland - Experience
- Minimum of 7 years in semiconductor technology roles; preferably in packaging integration, advanced packaging research, heterogeneous integration, process integration, package development, or related semiconductor process.
- Education
- Master’s degree in a related engineering or science discipline; Ph.D. preferred.
About the job
Leads advanced packaging integration research and multidisciplinary teams to develop, validate, and transfer next-generation heterogeneous semiconductor technologies into development or manufacturing.
What you'll do
- Set research strategy, technical roadmaps, milestones, and decision criteria for advanced packaging integration.
- Lead feasibility studies, prototyping, experimental validation, reliability assessments, and manufacturing readiness reviews.
- Manage cross-functional research teams and partnerships, and communicate technical progress, risks, and recommendations to leaders.
What they ask for
- Demonstrated experience leading advanced technology research programs, multidisciplinary teams, cross-functional initiatives, or external research collaborations.
- Strong understanding of package-system integration and related technologies, reliability, and manufacturability trade-offs.
- Ability to turn ambiguous integration challenges into hypotheses, experimental plans, measurable milestones, and recommendations.
- Strong communication skills for technical, executive, and cross-functional audiences.
Nice to have
- Innovation record in semiconductor packaging integration or related advanced packaging technologies.
- Experience with research-to-development transfer, technology readiness, pathfinding, prototype builds, or early manufacturing feasibility.
Pay
$220,920.00-311,890.00 USD (target compensation; posting does not specify base salary or total pay)
Tools
heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, interposer technology, fan-out, high-speed I/O
Model-written summary · the original posting is authoritative