Intel
Senior Analog and Mixed Signal Design Engineer
$142K–$269K
US, Oregon, Hillsboro +1 · Senior · Full-time · Posted Oct 26, 2026
- Location
- US, Oregon, Hillsboro
US, California, Santa Clara - Experience
- 6+ years with a bachelor’s degree, 4+ years with a master’s degree, or 2+ years with a Ph.D. in high-speed wireline SerDes circuit design.
- Education
- Bachelor’s, master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering.
About the job
Own SerDes link architecture and circuit design for Intel test chips, from system modeling and transistor-level implementation through silicon validation and process co-optimization.
What you'll do
- Define SerDes architecture, link budgets, channel analysis, and equalization strategy for next-generation interfaces.
- Model links and lead design, integration, tapeout, silicon bring-up, and correlation of measured results with simulations.
- Translate SerDes needs into process and PDK requirements; provide technical leadership and mentorship.
What they ask for
- Transistor-level design experience in SerDes TX, RX, or clocking circuits for at least one silicon-proven design at 28 Gb/s per lane or higher.
- Experience in at least one of: SerDes link architecture and analysis; high-speed link lab validation; behavioral or statistical link modeling in MATLAB or Python.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering plus 6+ years of relevant industry experience; or master’s plus 4+ years; or Ph.D. plus 2+ years.
Nice to have
- Silicon-proven designs at 56 Gb/s PAM4 or higher, in FinFET or GAA CMOS; multiple tape-outs with block ownership.
- Experience across architecture, lab validation, and link modeling.
Pay
$141,910.00-269,100.00 USD (annual target compensation; base salary or total pay not specified)
Tools
MATLAB, Python, COM, IBIS-AMI, PAM4, PCIe, UCIe, HBM
Model-written summary · the original posting is authoritative