Drimva

Intel

Senior CPU Front End Methodology Engineer

$164K–$312K

US, Texas, Austin +2 · Senior · Full-time · Posted Aug 13, 2026

Location
US, Texas, Austin
US, Arizona, Phoenix
US, Oregon, Hillsboro
Experience
Education-linked alternatives: bachelor’s degree plus 8+ years, master’s degree plus 7+ years, or PhD plus 4+ years; also requires 6+ years in CPU-logic silicon development and 5+ years in technical leadership and successful IP-project delivery.
Education
Bachelor’s, master’s, or PhD in Computer Science, Electrical, Electronics, Engineering, or a related field.

About the job

Leads CPU RTL front-end methodology and silicon-development improvements, including applying AI tools to improve coding efficiency and delivering designs that meet product targets.

What you'll do

  • Advance front-end methodologies and contribute to architectural and microarchitectural discussions.
  • Develop RTL-development and logic-optimization strategies, tools, and techniques to meet power, performance, area, timing, and physical-design targets.
  • Collaborate across architecture and design teams, providing technical leadership and applying AI tools to silicon development.

What they ask for

  • 6+ years of experience in silicon development of CPU logic.
  • 5+ years of experience in technical leadership and delivering successful IP projects.
  • Bachelor’s degree in a related field with 8+ years of work experience, or master’s degree with 7+ years, or PhD with 4+ years.
  • Excellent problem-solving, analytical, written, and verbal communication skills; ability to work effectively in fast-paced, collaborative environments.

Nice to have

  • Experience with x86 CPU microarchitecture or x86 memory management execution.
  • Experience driving front-end methodologies and applying AI tools for product-level benefits.

Pay

$164,470.00-311,890.00 USD (total compensation)

Tools

RTL, AI

AI focus

Leverage AI tools and methodologies to improve efficiency in RTL coding and other silicon-development areas, with tangible product-level benefits.

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 4, 2026 (UTC)