Intel
Senior Design Verification Engineer
$164K–$312K
US, California, Santa Clara · Senior · Full-time · Posted Jul 16, 2026
- Experience
- 10+ years in design verification.
- Education
- Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field.
About the job
Own end-to-end verification of Intel Silicon Chassis interconnect and IP blocks, from planning through signoff, while driving coverage, quality, and delivery.
What you'll do
- Plan and execute verification for IP features and subsystem integration; build reusable testbenches, checkers, VIPs, and behavioral models.
- Drive simulation and formal verification convergence, coverage closure, and functional signoff; contribute to performance and power goals.
- Collaborate with architecture, design, and software teams; lead IP delivery and mentor verification engineers.
What they ask for
- Bachelor of Science in Electrical or Computer Engineering, Computer Science, or a STEM-related field.
- 10+ years of design verification experience, including IP DV and subsystem- and SoC-level verification.
- Experience with interconnects, caches, memory subsystems, bus protocols, cache coherency, and memory consistency models.
- Experience with verification methodologies and tools including UVM, SVA, ABV, co-simulation, and low-power verification; coding experience in SystemVerilog/UVM, C/C++, Python, and build systems.
Nice to have
- Postgraduate degree in Electrical or Computer Engineering, Computer Science, or a STEM-related field.
- Experience with JasperGold, VC Formal, emulation or FPGA-based verification, or system IPs such as MMUs and interrupt controllers.
Pay
$164,470.00-311,890.00 USD (total compensation target range)
Tools
AMBA (CHI, ACE, AXI), PCIe, UCIe, CXL, UVM, SVA, SystemVerilog, Python
AI focus
Use AI-assisted development tools in everyday work and evaluate ML-driven verification flows.
Model-written summary · the original posting is authoritative