Intel
Senior DFT Logic Design Engineer
$142K–$269K
US, Arizona, Phoenix +2 · Senior · Full-time · Posted Sep 14, 2026
- Location
- US, Arizona, Phoenix
US, California, Santa Clara
US, Oregon, Hillsboro - Experience
- 3+ years with advanced CMOS processes and ASIC DFT/DFM implementation; 4+ years with one or more scripting languages.
- Education
- Bachelor's degree in Electrical / Computer Engineering, Computer Science, or a STEM-related field.
- Visa sponsorship
- US citizenship required; ability to obtain a US Government Security Clearance.
About the job
Provides technical support to Intel Foundry customers on DFT/DFM insertion, ATPG validation methods and flows, and design issues through successful tape-outs.
What you'll do
- Collaborate with Intel teams, customers, IP providers, and EDA vendors to resolve design issues.
- Develop technical content and deliver training and presentations.
- Improve and support ASIC DFT/DFM and ATPG validation methodologies, flows, and documentation at block and SoC levels.
What they ask for
- US citizenship and ability to obtain a US Government Security Clearance.
- Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or a STEM-related field.
- 3+ years of experience with advanced CMOS processes (16nm and below).
- 3+ years implementing ASIC DFT/DFM insertion and performing ATPG validation, DFT timing, and DFT signoff; 4+ years with one or more scripting languages.
Nice to have
- Active US Government Security Clearance at minimum Secret level; postgraduate degree in a relevant field.
- Experience with major EDA tool suites, DFT/DFM flows, customer support, or semiconductor foundry work.
Pay
$141,910.00-269,100.00 USD (target compensation; salary type not specified)
Tools
Python, Perl, Tcl, shell scripting, MBIST, LBIST, SCAN, JTAG
AI focus
Supports foundry customers and DFT/DFM work for semiconductor products serving AI-era applications; no specific AI development duties are stated.
Model-written summary · the original posting is authoritative