Intel
Senior PDK Physical Verification Engineer
$150K–$285K
US, Oregon, Hillsboro +3 · Senior · Full-time · Posted Oct 28, 2026
- Location
- US, Oregon, Hillsboro
US, California, Santa Clara
US, Texas, Austin
US, Arizona, Phoenix - Experience
- Bachelor’s degree: 6+ years of relevant experience; Master’s degree: 5+ years; PhD: 2+ years. Also requires 4+ years with a physical-verification platform and 3+ years with physical-verification rule decks.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; or Master’s degree; or PhD.
About the job
Develops and deploys density-fill methodologies and PDK physical-verification solutions for advanced semiconductor technologies, including automation, validation, and collaboration with engineering teams and EDA vendors.
What you'll do
- Lead development, implementation, and validation of density-fill solutions within advanced PDKs.
- Develop algorithmic physical-verification solutions, rule decks, and validation frameworks for manufacturability and density compliance.
- Collaborate with internal engineering teams and external EDA vendors, and provide technical documentation and training.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience; or a Master’s degree with 5+ years; or a PhD with 2+ years.
- 4+ years of hands-on experience with an industry-standard physical verification platform, including methodology development, rule-deck debugging, validation, or production deployment.
- 3+ years developing, maintaining, or debugging physical-verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based verification environments.
- Experience with semiconductor process technology, device physics, design rules, manufacturability, algorithmic solutions for advanced technology nodes, and Unix/Linux environments.
Nice to have
- 4+ years developing, deploying, or supporting density-fill methodologies for advanced semiconductor technologies at 16nm and below.
- Expertise in fill-rule implementation, density optimization, physical-verification flows, or solutions for foundry, IDM, or advanced process technologies.
Pay
$149,600.00-284,580.00 USD (total compensation)
Tools
Calibre, Synopsys ICV, Cadence Pegasus, SVRF, TVF, PXL, PVL, Tcl
Model-written summary · the original posting is authoritative