Intel
Sr. EDA Tools Engineer - PERC ESD
$150K–$285K
US, Oregon, Hillsboro +3 · Senior · Full-time · Posted Oct 8, 2026
- Location
- US, Oregon, Hillsboro
US, California, Santa Clara
US, Texas, Austin
US, Arizona, Phoenix - Experience
- 2+ years in ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools); 2+ years in scripting for QA and flow automation. Preferred: 4+ years with reliability/DRC tools.
- Education
- Master's degree or PhD in Electrical Engineering or Computer Engineering.
About the job
Develop and validate ESD/LU rule decks, methodologies, and automation for Intel process technologies, collaborating with design, reliability, CAD, and EDA vendor teams.
What you'll do
- Develop ESD/LU rule decks and maintain reliability design-rule methodologies and specifications.
- Build and execute test cases for debugging, validation, and signoff; define QA requirements and automate rule checks.
- Analyze ESD/LU design problems and lead improvements to verification tools and methodologies.
What they ask for
- Master's degree or PhD in Electrical Engineering or Computer Engineering.
- 2+ years' experience with ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools).
- 2+ years' experience in scripting (e.g., Python, Tcl, Perl, or similar) for QA and flow automation.
Nice to have
- 4+ years' experience with reliability/DRC tools.
- Knowledge of ESD/LU PreSi models (HBM, CDM), I/O design, and related methodologies.
Pay
$149,600.00-284,580.00 USD (annual target compensation)
Tools
ESD PERC, Python, Tcl, Perl, HBM, CDM
Model-written summary · the original posting is authoritative