Intel
System Technology Research Engineer - (PhD Intern)
$142K–$142K
US, Oregon, Hillsboro +2 · Internship · Posted Sep 14, 2026
- Location
- US, Oregon, Hillsboro
US, California, Santa Clara
US, Texas, Austin - Experience
- 1–2+ years of relevant research experience; internship is at least 3 months during summer 2026, with possible extension based on business needs.
- Education
- Active Ph.D. candidacy in a specified or similar area of study.
About the job
Research semiconductor system technology and evaluate 3D/2.5D memory and logic stacking schemes to support Intel’s packaging and processing roadmap.
What you'll do
- Develop and enhance System Technology Co-optimisation (STCO) methodologies.
- Evaluate devices, interconnects, materials, systems, and integration schemes at the system level.
- Collaborate with cross-functional teams on semiconductor and packaging innovation.
What they ask for
- Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design, or a similar area.
- 1–2+ years of relevant research experience in one or more listed technical areas.
- Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsis Fusion Compiler.
Nice to have
- Experience with IC design, simulation, physical layout, or tapeout; DRAM/SRAM design; manufacturing flows; or 2.5D/3D packaging.
- 3DIC design and simulation experience or programming skills, preferably in Python.
Pay
$141,998.00-142,002.00 USD (total compensation)
Tools
Cadence Virtuoso, Synopsis Fusion Compiler, Python
Model-written summary · the original posting is authoritative