Drimva

Intel

Transistor Reliability and Quality Engineer

$156K–$220K

US, Oregon, Hillsboro · Full-time · Posted Aug 27, 2026

Experience
6+ years with a bachelor’s degree, 4+ years with a master’s degree, or 2+ years with a Ph.D.
Education
Bachelor’s degree in Electrical Engineering, Materials Science, Physics, or a related field; master’s or Ph.D. in the above fields accepted.

About the job

Develops and qualifies transistor reliability methods, models, test structures, and data-analysis automation for Intel’s process technologies, from early development through manufacturing readiness.

What you'll do

  • Lead transistor reliability characterization and certification, including HCI, NBTI/PBTI, and TDDB.
  • Develop reliability models, test structures, monitors, and FMEA for transistor technologies.
  • Improve automation for analyzing high-volume reliability data and collaborate on process integration and design-for-reliability.

What they ask for

  • Bachelor’s degree in Electrical Engineering, Materials Science, Physics, or a related field; or a Master’s or Ph.D. in these fields.
  • Hands-on semiconductor device fabrication, process characterization, and experimental design experience.
  • Proficiency in statistical analysis and data interpretation using tools such as JMP, R, SAS, or Python.
  • Strong background in semiconductor device physics and reliability mechanisms; knowledge of process integration and technology development methodologies.

Nice to have

  • Semiconductor reliability engineering and technology qualification experience; familiarity with advanced CMOS integration and mechanisms such as HTOL, ELFR, and TDDB.
  • Experience with statistical quality systems, defect reliability modeling, failure analysis, physical characterization, data analytics, machine learning, AI-assisted workflows, or SQL/Python automation.

Pay

$155,520.00-219,550.00 USD (base salary)

Tools

JMP, R, SAS, Python, SQL, SPICE

AI focus

Preferred background in data analytics, machine learning, and AI-assisted engineering workflows.

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 4, 2026 (UTC)