K2 Space
Principal ASIC Design Verification Engineer
$190K–$285K
United States - Remote +1 · Remote · Principal · Full-time · Posted Jun 26, 2026
- Location
- United States - Remote
Los Angeles - Experience
- 10+ years of experience in ASIC/SoC verification.
- Education
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a U.S. person as defined by ITAR or otherwise eligible for a federally issued export control license.
About the job
Verify custom ASIC designs across block, subsystem, and full-chip levels, shaping verification methods and supporting silicon bring-up and validation.
What you'll do
- Develop verification plans and SystemVerilog/UVM testbenches; drive testing, coverage closure, and regression management.
- Debug simulation failures, collaborate across design teams, and contribute to design reviews and design-for-verification practices.
- Support post-silicon validation and advance verification methodologies; lead complex systems as needed.
What they ask for
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of experience in ASIC/SoC verification.
- Experience with SystemVerilog, UVM, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with simulation and debug tools, regression and CI/CD automation, gate-level simulation, reference models, embedded processor designs, and post-silicon validation.
Nice to have
- Experience with low power verification or analog behavioral models.
- Familiarity with physical design flows or experience in space, telecom, or RF/digital mixed systems.
Pay
$190,000 – $285,000 USD base salary
Tools
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, SimVision, Python
Model-written summary · the original posting is authoritative