K2 Space
Principal ASIC Design Verification Engineer
$190K–$285K
Seattle, WA +1 · Principal · Full-time · Posted Jun 30, 2026
- Location
- Seattle, WA
Seattle, Washington, United States - Experience
- 10+ years in ASIC/SoC verification.
- Education
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by ITAR or otherwise eligible for a federally issued export control license.
About the job
Verify custom ASIC designs across block, subsystem, and full-chip levels, shaping verification methodology and supporting silicon bring-up and validation.
What you'll do
- Develop verification plans and SystemVerilog/UVM testbenches; write assertions and use formal verification where appropriate.
- Run simulations and regressions, analyze failures, and drive coverage closure and root-cause resolution.
- Collaborate across design teams, advance verification methods, and support post-silicon validation.
What they ask for
- 10+ years of experience in ASIC/SoC verification.
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Strong knowledge of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Experience with UVM testbenches, constrained-random testing, coverage, assertions, regression management, reference models, and post-silicon validation.
Nice to have
- Experience with low-power verification or analog behavioral models.
- Familiarity with physical design flows; space, telecom, or RF/digital mixed-systems experience is a plus.
Pay
$190,000 – $285,000 USD base salary
Tools
SystemVerilog, UVM, SVA, VCS, Xcelium, Questa, Verdi, Python
Model-written summary · the original posting is authoritative