K2 Space
Principal ASIC Physical Design Engineer
$190K–$280K
United States - Remote +1 · Remote · Principal · Full-time · Posted Jul 1, 2026
- Location
- United States - Remote
Los Angeles - Experience
- 10+ years of experience in ASIC physical design for high-performance SoCs.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Leads end-to-end physical design of complex SoCs for satellite and space systems, from RTL handoff through GDSII sign-off and production support.
What you'll do
- Own RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, CTS, STA, physical verification, and sign-off.
- Develop physical design methods and automation; drive PPA optimization and timing closure across process and voltage corners.
- Coordinate design teams, external partners, EDA vendors, package/test teams, and post-silicon support through integration and bring-up.
What they ask for
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- End-to-end RTL-to-GDSII expertise using Synopsys, Cadence, or Siemens tools.
- Hands-on timing closure, IR drop analysis, ECO implementation, and advanced FinFET experience.
- Experience coordinating outsourced physical design teams or vendors.
Nice to have
- Exposure to radiation-hardened or space-qualified ASICs.
- Experience with chip-package co-design or advanced packaging (2.5D/3D).
Pay
$190,000 – $280,000 USD base salary
Tools
Synopsys, Cadence, Siemens, FinFET, UPF/CPF, TSMC, Gate-All-Around
Model-written summary · the original posting is authoritative