K2 Space
Principal ASIC Physical Design Engineer
$190K–$280K
Seattle, WA +1 · Principal · Full-time · Posted Jun 30, 2026
- Location
- Seattle, WA
Seattle, Washington, United States - Experience
- 10+ years in ASIC physical design for high-performance SoCs.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Leads end-to-end physical design of advanced SoCs for satellite and space systems, from RTL handoff through GDSII sign-off and production support.
What you'll do
- Own RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, CTS, STA, physical verification, and sign-off.
- Develop physical-design methodologies and automation, drive timing closure and PPA optimization, and coordinate with design, packaging, test, and EDA teams.
- Guide external design partners and support chip bring-up, production, and spaceflight.
What they ask for
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of ASIC physical design experience for high-performance SoCs.
- End-to-end RTL-to-GDSII expertise using Synopsys, Cadence, or Siemens tools; hands-on timing closure, IR drop analysis, and ECO implementation.
- Experience with advanced FinFET nodes, multi-clock/multi-voltage/hierarchical SoCs, and managing or coordinating outsourced physical-design teams or vendors.
Nice to have
- Exposure to radiation-hardened or space-qualified ASICs; chip-package co-design or advanced packaging.
- Experience driving tapeouts through TSMC or with Gate-All-Around technologies.
Pay
$190,000 – $280,000 USD base salary
Tools
Synopsys, Cadence, Siemens, FinFET, UPF/CPF, TSMC, Gate-All-Around, GDSII
Model-written summary · the original posting is authoritative