K2 Space
Senior ASIC Design Verification Engineer
$170K–$250K
United States - Remote +1 · Remote · Senior · Full-time · Posted Jun 23, 2026
- Location
- United States - Remote
Los Angeles - Experience
- 5+ years of experience in ASIC/SoC verification.
- Education
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Verify custom ASIC designs across block, subsystem, and full-chip levels, contributing to verification methodology and supporting silicon bring-up.
What you'll do
- Develop verification plans and SystemVerilog/UVM testbenches; drive testing, assertions, and coverage closure.
- Run regressions and simulations, debug failures, and collaborate with RTL and cross-functional teams to resolve issues.
- Support design reviews, verification-methodology improvements, and post-silicon validation.
What they ask for
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in ASIC/SoC verification.
- Experience with SystemVerilog, UVM testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Proficiency with simulation and waveform-debug tools, scripting, regression and coverage workflows, Git, and CI/CD automation.
Nice to have
- Experience with reference models, low-power verification, gate-level simulation, analog behavioral models, or post-silicon validation.
- Experience in space, telecom, or RF/digital mixed systems.
Pay
$170,000 – $250,000 USD base salary
Tools
SystemVerilog, UVM, SVA, VCS, Xcelium, Questa, Verdi, SimVision
Model-written summary · the original posting is authoritative