K2 Space
Senior ASIC Design Verification Engineer
$170K–$250K
Seattle, WA +1 · Senior · Full-time · Posted Jun 30, 2026
- Location
- Seattle, WA
Seattle, Washington, United States - Experience
- 5+ years of experience in ASIC/SoC verification.
- Education
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Verifies custom ASIC designs across block, subsystem, and full-chip levels, from verification planning and simulation through coverage sign-off and silicon validation.
What you'll do
- Develop verification plans and build SystemVerilog/UVM testbenches, assertions, and coverage models.
- Run and manage simulations and regressions; debug failures, analyze root causes, and collaborate with RTL designers on fixes.
- Contribute to design reviews and verification methodology, and support silicon bring-up and post-silicon validation.
What they ask for
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in ASIC/SoC verification.
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Proficiency with simulation and waveform-debug tools, coverage tools, and scripting languages; experience with regression management, Git, and CI/CD automation.
Nice to have
- Experience developing and integrating reference models; understanding of low-power verification or gate-level simulation.
- Experience with post-silicon validation, or space, telecom, or RF/digital mixed systems.
Pay
$170,000 – $250,000 USD base salary
Tools
SystemVerilog, UVM, SVA, VCS, Xcelium, Questa, Verdi, Python
Model-written summary · the original posting is authoritative