K2 Space
Senior ASIC Physical Design Engineer
$170K–$250K
Seattle, WA +1 · Senior · Full-time · Posted Jun 30, 2026
- Location
- Seattle, WA
Seattle, Washington, United States - Experience
- 5–10 years of experience in ASIC physical design for complex SoCs.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Implements advanced satellite SoCs from synthesis through GDSII, focusing on timing closure, PPA optimization, integration, and production and spaceflight support.
What you'll do
- Execute physical design, integration, timing closure, and sign-off activities for complex SoCs.
- Collaborate with internal teams and external providers to resolve design issues and align deliverables with schedules.
- Develop automation and methodologies, and support ECOs and tapeout preparation.
What they ask for
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Hands-on experience with Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent.
- Strong understanding of timing analysis, power optimization, and physical verification flows.
- Experience with hierarchical or flat SoC methodologies; familiarity with FinFET technologies; working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
Nice to have
- Exposure to radiation-hardened or space-qualified ASICs, advanced packaging, vendor management, TSMC sign-off, or Gate-All-Around technologies.
- Experience in cross-functional, geographically distributed teams.
Pay
$170,000 – $250,000 USD base salary
Tools
Synopsys ICC2/Fusion Compiler, Cadence Innovus, FinFET, DFT, UPF/CPF, TSMC, Gate-All-Around, DRC/LVS
Model-written summary · the original posting is authoritative