K2 Space
Senior ASIC Physical Design Engineer
$170K–$250K
United States - Remote +1 · Remote · Senior · Full-time · Posted Jul 1, 2026
- Location
- United States - Remote
Los Angeles - Experience
- 5–10 years of experience in ASIC physical design for complex SoCs.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Implements and integrates advanced SoCs for satellite systems, from synthesis through physical sign-off and tapeout, optimizing timing, power, and physical design.
What you'll do
- Execute physical design flows for SoC blocks and top-level integration, including floorplanning, place and route, timing analysis, and physical verification.
- Achieve timing closure and support sign-off, integration, engineering change orders, and tapeout preparation.
- Coordinate with internal teams and external design partners; develop automation and maintain design methodologies.
What they ask for
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Hands-on experience with industry-standard physical design tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
- Strong understanding of timing analysis, power optimization, and physical verification; experience with hierarchical or flat SoC design methodologies.
- Familiarity with FinFET technologies and working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
Nice to have
- Exposure to radiation-hardened or space-qualified ASICs; experience with chip-package co-design or advanced packaging (2.5D/3D).
- Experience with sign-off through TSMC or Gate-All-Around technologies.
Pay
$170,000 – $250,000 USD base salary
Tools
Synopsys ICC2/Fusion Compiler, Cadence Innovus, FinFET, DFT, UPF/CPF, TSMC, Gate-All-Around
Model-written summary · the original posting is authoritative