Drimva

K2 Space

Senior FPGA Prototyping Engineer

$120K–$225K

United States - Remote +1 · Remote · Senior · Full-time · Posted Aug 11, 2026

Location
United States - Remote
Los Angeles
Experience
5+ years of FPGA development experience.
Education
BS or MS in Electrical Engineering, Computer Engineering, or related field.
Visa sponsorship
Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

About the job

Own FPGA prototyping, firmware enablement, first-silicon bring-up, and hardware validation for next-generation communications ASICs.

What you'll do

  • Develop FPGA prototypes and hardware platforms for early ASIC integration, firmware development, and system validation; support first-silicon bring-up and debug.
  • Build automated validation infrastructure, FPGA traffic generators, protocol checkers, and test applications to validate interfaces and characterize silicon.
  • Debug across RTL, firmware, software, FPGA prototypes, and silicon, collaborating with engineering teams on product development.

What they ask for

  • 5+ years of FPGA development using Verilog/SystemVerilog and AMD/Xilinx FPGA tools.
  • Strong understanding of ASIC development and digital system architecture; experience with FPGA prototyping for ASIC development.
  • Experience with firmware/software enablement and hardware bring-up; strong debugging skills with JTAG, oscilloscopes, logic analyzers, and protocol analyzers.
  • Proficiency with Python and scripting for automation and test infrastructure.

Nice to have

  • Experience with networking, communications, or satellite systems; embedded processors (ARM or RISC-V); or hard real-time embedded systems.
  • Experience validating high-speed digital interfaces, including Ethernet and SerDes protocols, SPI, and UART.

Pay

$120,000 – $225,000 USD base salary

Tools

Verilog, SystemVerilog, AMD/Xilinx FPGA tools, Python, JTAG, Ethernet SerDes, SPI, UART

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)