K2 Space
Senior Serdes Characterization & Post-Silicon Validation Engineer
$170K–$250K
Los Angeles, CA +1 · Senior · Full-time · Posted Sep 17, 2026
- Location
- Los Angeles, CA
Los Angeles - Experience
- 5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
- Education
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Brings up, characterizes, and validates high-speed SerDes interfaces from first silicon through product integration and system-level operation, while building test and validation capabilities.
What you'll do
- Lead post-silicon bring-up and electrical characterization of NRZ and PAM4 SerDes, including 112G-class interfaces.
- Debug and validate links across silicon, firmware, package, PCB, and system boundaries; correlate measurements with models and simulations.
- Build automated characterization, regression, and lab infrastructure for measurement, analysis, and reporting.
What they ask for
- Strong understanding of high-speed serial-link fundamentals, including signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
- Hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
- Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
- Strong debugging skills across silicon, package, PCB, firmware, and system boundaries.
Nice to have
- Experience with 112G+ PAM4 SerDes characterization and validation.
- Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
Pay
$170,000 – $250,000 USD base salary
Tools
NRZ, PAM4, FFE, CTLE, DFE, Python, BERTs, VNAs
Model-written summary · the original posting is authoritative