K2 Space
Senior Serdes Characterization & Post-Silicon Validation Engineer
$170K–$250K
Seattle, WA +1 · Senior · Full-time · Posted Sep 17, 2026
- Location
- Seattle, WA
Seattle, Washington, United States - Experience
- 5+ years in high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
- Education
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- Visa sponsorship
- Must be a U.S. person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
About the job
Brings up, characterizes, and validates high-speed SerDes interfaces in complex SoCs, from first silicon through product integration and system-level operation.
What you'll do
- Lead post-silicon bring-up and electrical characterization of NRZ and PAM4 SerDes, including BER, signal quality, equalization, and link-margin testing.
- Debug link issues across SerDes IP, clocks, power, packaging, boards, firmware, and digital logic; correlate measurements with models and simulations.
- Build automated test and regression environments and help establish the high-speed validation lab and infrastructure.
What they ask for
- BS/MS in Electrical Engineering, Computer Engineering, or a related field.
- Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4, equalization, CDR, jitter, BER, channel loss, and link budgets.
- Hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
- Experience automating characterization with Python or similar scripting languages and instrument-control interfaces.
Nice to have
- Experience characterizing and validating 112G+ PAM4 SerDes.
- Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
Pay
USD 170,000 – USD 250,000 base salary
Tools
NRZ, PAM4, Python, FFE, CTLE, DFE, BERTs, VNAs
Model-written summary · the original posting is authoritative