Drimva

Lightmatter

Analog IC Design Engineer, High-Speed

Toronto, ON +2 · Full-time · Posted Mar 24, 2025

Location
Toronto, ON
Boston, MA
Mountain View, CA
Experience
MS with 6+ years of industry experience, OR Ph.D. with 3+ years of industry experience, focused on optical or wireline transceiver design.
Education
MS or Ph.D.
Visa sponsorship
Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.

About the job

Design and validate high-speed analog/mixed-signal transceiver circuits for optical and wireline communication systems, including interfaces to silicon photonics.

What you'll do

  • Develop micro-architecture feasibility studies and collaborate on electrical requirements.
  • Design analog/mixed-signal transceiver and broadband circuits; document simulations and verification for design reviews.
  • Run integration simulations, drive floorplan and mask-view reviews, define test plans, and validate circuits in the lab.

What they ask for

  • Experience designing GHz-speed RF or broadband analog circuits.
  • Experience with Tx/Rx equalization techniques and circuits; familiarity with SERDES architectures and implementations.
  • Solid understanding of CMOS device characteristics, noise, mismatch, linearity, and design trade-offs.
  • Experience with Cadence Design Environment and ability to collaborate across functional areas.

Nice to have

  • Experience designing transceiver Analog-Front-End blocks such as TIAs and Tx Drivers; testing and validating high-speed analog/mixed-signal circuits; or interfacing with silicon photonic modulators.
  • Knowledge of 3D Electro-Magnetic (EM) simulation tools or a record of delivering analog/mixed-signal IPs successfully on tight schedules.

Pay

$135,000 — $180,000 CAD (base salary)

Tools

Cadence Design Environment, SERDES, CMOS, 3D Electro-Magnetic (EM) simulation tools, TIA, Tx Driver, MZM, Ring

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)