Lightmatter
Sr. Staff Physical Design Engineer
$217K–$267K
Boston, MA +2 · Senior Staff · Full-time · Posted Jul 24, 2026
- Location
- Boston, MA
Mountain View, CA
Toronto, ON - Experience
- 12+ years; alternatively, preferred qualification: a master’s degree with 8 years of industry experience.
- Education
- Bachelor’s in Electrical Engineering or Computer Engineering.
- Visa sponsorship
- Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.
About the job
Implement and optimize complex digital ASIC blocks, driving physical design, timing closure, power integrity, and verification in advanced process nodes.
What you'll do
- Implement digital blocks from synthesis through physical verification; drive full-chip STA signoff and timing ECOs.
- Perform power analysis and optimization, floor planning, IO placement, and clock distribution.
- Debug DRC/LVS and write scripts to automate or customize design flows.
What they ask for
- Bachelor’s in Electrical Engineering or Computer Engineering.
- 12+ years of industry experience as a Physical Design Engineer.
- Completed block or top-level physical design for large ASICs or mixed-signal chips that taped out.
- Thorough knowledge of timing closure and LVS/DRC closure; experience with TCL and Python or other scripting languages.
Nice to have
- Master’s in Electrical Engineering or Computer Engineering with 8 years of industry experience; hands-on Cadence tools experience.
- 3nm tape-out experience; EM/IR analysis using standard industry signoff tools; willingness to do manual layouts and learn silicon photonics layout.
Pay
$217,000 — $267,000 USD (total compensation; the posting describes a base salary range but labels this amount under total compensation).
Tools
TCL, Python, Shell, Cadence
AI focus
The role implements physical design for high-performance ASICs used in AI and HPC infrastructure; no direct AI development work is stated.
Model-written summary · the original posting is authoritative