Lightmatter
Sr. Staff Physical Design Timing Engineer (STA)
$217K–$267K
Boston, MA +2 · Senior Staff · Full-time · Posted Jun 9, 2026
- Location
- Boston, MA
Mountain View, CA
Toronto, ON - Experience
- 12 years of Physical Design experience; minimum 5 years of hands-on ASIC STA, timing constraints development, and timing closure. Preferred: minimum 8 years of hands-on experience in those areas.
- Education
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- Visa sponsorship
- Candidates should have capacity to comply with federally mandated U.S. export control requirements.
About the job
Drive static timing analysis, timing constraints, and timing closure through tapeout for Lightmatter’s silicon photonics chips.
What you'll do
- Lead STA sign-off, full-chip timing analysis, and timing closure across technology nodes and scenarios.
- Develop timing constraints and sign-off methodologies with architecture, RTL, DFT, and methodology teams.
- Automate timing ECO generation and guide chip implementation tradeoffs across power, performance, and area.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 12 years of Physical Design experience, including at least 5 years hands-on in ASIC STA, timing constraints, and timing closure with Cadence or Synopsys tools.
- Experience with on-chip variation derates, multi-mode multi-corner constraints, and clock tree strategies.
- Scripting experience with TCL and Python, PERL, or Shell.
Nice to have
- Master’s degree in Electrical Engineering or Computer Engineering.
- At least 8 years of hands-on experience in ASIC STA, timing constraints, and timing closure with Cadence or Synopsys tools.
Pay
$217,000 — $267,000 USD (total compensation; the posting does not specify whether this range is base salary or total pay)
Tools
Cadence, Synopsys, TCL, Python, PERL, Shell, Tempus, PrimeTime
Model-written summary · the original posting is authoritative