Lightmatter
Sr. Staff Physical Design Timing Engineer (STA)
$220K–$270K
Mountain View, CA +1 · Senior Staff · Full-time · Posted Nov 3, 2025
- Location
- Mountain View, CA
Toronto, ON - Experience
- 12 years of Physical Design experience; minimum 5 years hands-on in ASIC STA, timing constraints development, and timing closure. Preferred: minimum 8 years hands-on in those areas.
- Education
- Bachelor’s degree in Electrical Engineering or Computer Engineering; a Master’s degree is preferred.
- Visa sponsorship
- Candidates should have capacity to comply with federally mandated U.S. export control requirements.
About the job
Drive timing constraints development, static timing analysis (STA), timing closure, and signoff for silicon photonics chips across technology nodes and implementation flows.
What you'll do
- Lead STA signoff, full-chip timing analysis, and timing-summary projections across scenarios.
- Develop timing modes and constraints with architecture, RTL, DFT, and methodology teams; incorporate signoff corners, margins, and derates.
- Use Tempus/PrimeTime to automate timing ECOs and support timing closure and physical design implementation.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 12 years of Physical Design experience, including at least 5 years of hands-on ASIC STA, timing constraints development, and timing closure with Cadence or Synopsys tools.
- Experience managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing clock tree strategies.
- Proficiency in TCL and at least one of Python, PERL, or Shell; strong problem-solving and communication skills.
Nice to have
- Master’s degree in Electrical Engineering or Computer Engineering.
- At least 8 years of hands-on ASIC STA, timing constraints development, and timing closure experience with Cadence or Synopsys tools.
Pay
$220,000 — $270,000 USD (total compensation; the posting does not specify this as base salary)
Tools
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
AI focus
Supports photonics-based interconnect chips for AI and HPC data-center workloads; the role focuses on physical design timing, not AI development.
Model-written summary · the original posting is authoritative