MatX
Micro-Architect and RTL Designer
$160K–$600K
Mountain View (HQ) or Remote · Hybrid · Full-time · Posted Jun 15, 2026
- Experience
- 4 years or more with SystemVerilog, Python, C/C++, and similar scripting and programming languages; concept-to-silicon experience is also required, with no specific duration stated.
- Visa sponsorship
- Employment is contingent on the applicant being able to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
About the job
Design and deliver high-performance, functionally accurate silicon for compute, memory management, connectivity, and other MatX products, from micro-architecture through sign-off and tapeout.
What you'll do
- Contribute to scalable silicon architecture-to-design methodology across blocks, subsystems, and full-chip design.
- Own subsystem or chip-level design deliverables from micro-architecture to sign-off-ready design; drive reviews and progress toward area and timing closure, design freeze, and tapeout.
- Collaborate with verification, DFT, and physical design teams to achieve performance, power, and area goals.
What they ask for
- Concept-to-silicon experience taking ASIC or SoC subsystems or top-level functions from architecture specification to production silicon.
- 4 years or more experience with SystemVerilog, Python, C/C++, and similar chip-design scripting and programming languages.
- Production-proven silicon micro-architecture and design experience in high-performance compute, high-speed connectivity, memory management, or related functionality.
- Experience testing designs and collaborating with verification teams on performance and coverage closure; hands-on design synthesis and lint experience.
Nice to have
- Familiarity with verification and emulation platforms and methodologies.
- Experience with high-speed I/O IP or logic for moving, storing, or managing data, such as caches, buffers, and crossbars.
Pay
$160,000 - $275,000 USD base salary; $175,000 - $400,000 USD base salary; $250,000 - $600,000 USD base salary
Tools
SystemVerilog, Python, C/C++, ASICs, SOCs
Model-written summary · the original posting is authoritative