MatX
PCB Layout Engineer - AI Compute Hardware
$160K–$600K
Mountain View (HQ) or Remote · Hybrid · Full-time · Posted Aug 28, 2026
- Experience
- 7+ years.
- Visa sponsorship
- Employment is contingent on the applicant being able to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
About the job
Designs and releases high-speed, high-power, high-density PCBs for AI chips, compute trays, and rack-scale systems.
What you'll do
- Own PCB layout from floorplanning through Gerber release, including stack-ups, BGA routing, and power delivery networks.
- Route high-speed interfaces and meet signal- and power-integrity requirements; incorporate simulation feedback.
- Coordinate DFM reviews and fabrication releases with mechanical engineers, PCB fabricators, and JDM/ODM partners; support bring-up and debug.
What they ask for
- 7+ years of PCB layout experience, including complex 20+ layer boards for server, AI compute, networking, or similar high-performance hardware.
- Strong proficiency in Cadence Allegro or equivalent EDA tool and expertise in high-speed design.
- Experience with fine-pitch BGA layout and interfaces including PCIe Gen5/6, CXL, DDR5, or 112G/224G SerDes.
- Understanding of PDN and stack-up design, advanced fabrication techniques, DFM/DFT, and interpreting SI/PI simulation results.
Nice to have
- Experience with 5nm or 3nm-and-below AI ASIC board layout, or 224G PAM4 routing.
- Familiarity with OCP Open Rack, power integrity simulation tools, fiber weave mitigation, or EMI/EMC design.
Pay
$160,000 - $275,000 USD base salary; $175,000 - $400,000 USD base salary; $250,000 - $600,000 USD base salary
Tools
Cadence Allegro, PCIe Gen5/6, CXL, DDR5, 112G/224G SerDes, Megtron 6/8/9, TU-953Q, Ansys SIwave
AI focus
PCB layout for AI ASICs and AI compute infrastructure used for large-scale LLM training and inference.
Model-written summary · the original posting is authoritative