MatX
Silicon Design-for-Test (DFT) Engineer
$160K–$600K
Mountain View (HQ) or Remote · Hybrid · Full-time · Posted Dec 19, 2024
- Visa sponsorship
- Employment is contingent on the applicant being able to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
About the job
Implements and verifies design-for-test functions for MatX silicon, including SERDES PHY test and SoC-level test integration, from design through silicon bring-up.
What you'll do
- Develop SERDES PHY functional test solutions and integrate PHY DFT interfaces into SoC test architecture.
- Implement and verify block-level DFT, including scan closure, ATPG pattern generation, and sign-off.
- Support silicon test-program bring-up and analyze test escapes to improve DFT coverage and test quality.
What they ask for
- Hands-on DFT implementation experience with MBIST, at-speed scan, and scan compression.
- Knowledge of JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
- Experience or working knowledge of loading and validating PHY firmware via SPI, I2C, or JTAG.
- Experience integrating PHY DFT interfaces into SoC DFT architecture.
Nice to have
- System-level DFT access experience, including hierarchical test access, test data compression, and multi-die/chiplet DFT.
- Familiarity with Synopsys DFT Compiler, Mentor Tessent, or equivalent.
Pay
$160,000 - $275,000 USD base salary; $175,000 - $400,000 USD base salary; $250,000 - $600,000 USD base salary
Tools
SERDES PHY, SPI, I2C, JTAG, Synopsys DFT Compiler, Mentor Tessent, ATE, ATPG
Model-written summary · the original posting is authoritative