MatX
SoC Design Verification Engineer
$160K–$600K
Mountain View (HQ) or Remote · Hybrid · Full-time · Posted Feb 16, 2024
- Experience
- Concept-to-silicon experience is required; no number of years is stated.
- Visa sponsorship
- Employment is contingent on the applicant’s ability to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
About the job
Develop and execute verification for MatX silicon across subsystems and chip-level systems, from verification planning through coverage closure and tapeout.
What you'll do
- Contribute to scalable verification methodology across blocks, subsystems, full chip, and system-level validation.
- Own subsystem- and chip-level verification execution, including testbenches, tests, and coverage closure.
- Plan and drive verification reviews and closure toward silicon milestones, including design freeze and tapeout.
What they ask for
- Concept-to-silicon experience driving verification from architecture or design specifications to production silicon.
- Experience with SystemVerilog, Python, C/C++, Bluespec, and similar verification or modeling languages.
- Production experience with UVM and assertion-based verification; formal and simulated verification experience is required.
- Production experience creating portable verification tests and drivers for silicon validation and post-silicon debug.
Nice to have
- Familiarity with emulation and prototyping platforms and methodologies.
- Hands-on participation in silicon debug and bring-up.
Pay
$160,000 - $275,000 USD base salary; $175,000 - $400,000 USD base salary; $250,000 - $600,000 USD base salary
Tools
SystemVerilog, Python, C/C++, Bluespec, UVM
AI focus
The role verifies silicon for high-performance, sustainable GenAI products; no direct AI model development work is stated.
Model-written summary · the original posting is authoritative