MatX
SOC Micro-Architect and RTL Designer
$160K–$600K
Mountain View (HQ) or Remote · Hybrid · Full-time · Posted May 19, 2026
- Experience
- 5+ years or more; concept-to-silicon experience taking ASICs or SoCs from architecture specification to production silicon.
- Visa sponsorship
- Employment is contingent on the applicant being able to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
About the job
Design and deliver high-performance silicon for compute, memory management, and connectivity, from micro-architecture through sign-off and tapeout.
What you'll do
- Develop scalable architecture-to-design methods across blocks, subsystems, and full-chip design; own design deliverables through sign-off.
- Plan and lead architecture and design reviews, tracking execution, area, and timing closure toward milestones and tapeout.
- Collaborate with verification, DFT, and physical design teams to achieve performance, power, area, and coverage goals.
What they ask for
- Concept-to-silicon experience taking ASICs or SoCs from architecture specification to production silicon.
- 5+ years of experience with SystemVerilog, Python, C/C++, and similar programming or scripting languages for chip design and related flows.
- Production-proven micro-architecture and design experience in high-performance compute, high-speed connectivity, memory management, or related functions.
- Hands-on experience with synthesis, equivalence checking, design lint, and clock-domain-crossing flows; experience with testing designs and verification teams.
Nice to have
- Familiarity with verification and emulation platforms; hands-on participation in silicon debug and bring-up.
- Hands-on silicon and firmware implementation experience with PCIe, HBM, DMA, or Die-to-die subsystems.
Pay
USD $160,000 - $275,000 base salary; USD $175,000 - $400,000 base salary; USD $250,000 - $600,000 base salary
Tools
SystemVerilog, Python, C/C++, PCIe, HBM, DMA, Die-to-die
AI focus
Design silicon for high-performance and sustainable GenAI workloads, including hardware for training and running large ML workloads.
Model-written summary · the original posting is authoritative