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ASIC Design Verification Engineer, DFT
$178K–$250K
Sunnyvale, CA +1 · Full-time · Posted Oct 13, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 8+ years in ASIC design verification and 8+ years in DFT verification.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
About the job
Verifies DFT architectures for custom ASICs and SoCs, driving pre-silicon verification closure and supporting silicon test bring-up.
What you'll do
- Define and execute DFT verification plans for scan, ATPG, BIST, JTAG, and boundary scan across IP, sub-system, and SoC levels.
- Develop UVM- and C/C++-based testbenches, drive coverage and verification closure, and debug DFT failures.
- Validate ATPG flows and use formal verification and emulation to support DFT bring-up and pre-/post-silicon correlation.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 8+ years of hands-on ASIC design verification experience using SystemVerilog and UVM-based methodologies.
- 8+ years of DFT verification experience, including scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1 test access mechanisms.
- Experience with DFT EDA tools, verification closure, and scripting in Python, Tcl, Perl, or Shell.
Nice to have
- DFT verification experience with AI/ML accelerator or networking ASICs in data center environments.
- Experience verifying PCIe, HBM, DDR, or Ethernet SerDes DFT structures, or using emulation platforms.
Pay
$178,000/year to $250,000/year USD base salary; bonus and equity also stated, amounts unspecified.
Tools
SystemVerilog, UVM, C/C++, Python, Tcl, Perl, Shell, IEEE 1149.1
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