Drimva

Meta

ASIC Engineer, Architecture Kernel Development

$146K–$209K

Sunnyvale, CA +1 · Full-time · Posted Oct 5, 2026

Location
Sunnyvale, CA
Austin, TX
Experience
6+ years in software development mapping massively parallel workloads for HPC or kernel development.
Education
Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience. A Master’s or PhD degree in Electrical Engineering, Computer Engineering, or related areas is also mentioned.

About the job

Develop AI kernels, performance-analysis tools, and compiler and ISA optimizations for Meta AI accelerators, helping validate accelerator performance through simulation and emulation.

What you'll do

  • Develop AI kernels for Meta AI models on Meta AI Accelerators.
  • Build static performance-analysis tools and debug performance on the dynamic performance simulator.
  • Identify compiler, ISA, and optimization approaches, and help validate performance on RTL simulation or emulation.

What they ask for

  • Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
  • 6+ years of experience in software development mapping massively parallel workloads for HPC or kernel development.
  • Programming experience in C, C++, Python, or related languages.
  • Experience with computer architecture or silicon-development tools; compute or collective kernel optimization using CUDA or similar models; GPU or AI accelerator architectures; and pre-silicon validation.

Nice to have

  • Master’s or PhD degree in Electrical Engineering, Computer Engineering, or related areas, with experience driving ML performance optimization and trade-offs.
  • Experience with firmware development, API design, device drivers, and library implementation.

Pay

$146,000/year to $209,000/year (base salary)

Tools

C, C++, Python, CUDA, SSE, AVX, NEON, Hexagon DSP

AI focus

Develop AI kernels for Meta AI models and contribute to machine-learning accelerator architecture and performance optimization.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 4, 2026 (UTC)