Meta
ASIC Engineer, Design
$178K–$250K
Sunnyvale, CA +2 · Remote · Full-time · Posted Sep 21, 2026
- Location
- Sunnyvale, CA
Remote, US
Austin, TX - Experience
- 8+ years for micro-architecture and RTL development for complex control and data path IPs; alternatively, experience in SoC Micro-architecture, Design and Integration (years not stated).
- Education
- Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
About the job
Designs ASICs for Meta’s Infrastructure organization, including chips for machine learning, video transcoding, and network acceleration.
What you'll do
- Explore architectures and develop micro-architectures.
- Identify, select, and integrate soft and hard IP; collaborate on test plans and debug with verification and emulation teams.
- Work with implementation teams to close designs on timing and power.
What they ask for
- Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs, or experience in SoC Micro-architecture, Design and Integration.
- RTL development using Verilog, System Verilog, and HLS; experience with CPU, NOC, Memory, and Peripheral Subsystems.
- Experience with Synthesis, Timing Closure, and Formal Verification Methodology.
Nice to have
- Master’s or PhD degree in Electrical Engineering, Computer Science, or related areas.
- Experience in data path development.
Pay
$178,000/year to $250,000/year USD base salary; bonus and equity (amounts not stated).
Tools
Verilog, System Verilog, HLS, CPU, NOC, Memory, Peripheral Subsystems
AI focus
ASICs for machine learning workloads.
Model-written summary · the original posting is authoritative