Meta
ASIC Engineer, Design
$114K–$172K
Sunnyvale, CA +1 · Full-time · Posted Sep 21, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 2+ years for micro-architecture and RTL development, or experience in SoC micro-architecture, design, and integration.
- Education
- Bachelor’s degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience; degree must be completed prior to joining Meta.
About the job
Designs ASICs for Meta’s infrastructure applications, including machine learning, video transcoding, and network acceleration.
What you'll do
- Explore architectures and develop micro-architectures.
- Identify, select, and integrate soft and hard IP; collaborate with verification and emulation teams on test plans and debug.
- Work with implementation teams to close designs on timing and power.
What they ask for
- Bachelor’s degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience; degree must be completed before joining.
- 2+ years of micro-architecture and RTL development for complex control and data path IPs, or experience in SoC micro-architecture, design, and integration.
- RTL development using Verilog, System Verilog, and HLS; experience in CPU, NOC, memory, and peripheral subsystems.
- Experience with synthesis, timing closure, and formal verification methodology.
Nice to have
- Master’s or PhD degree in Electrical Engineering, Computer Science, or related areas.
- Experience in data path development.
Pay
$114,000/year to $172,000/year USD base salary + bonus + equity
Tools
Verilog, System Verilog, HLS
AI focus
Designs ASICs for machine learning applications.
Model-written summary · the original posting is authoritative