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ASIC Engineer, Design for Test
$146K–$209K
Sunnyvale, CA +1 · Full-time · Posted Aug 15, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 6+ years.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
About the job
Architects and implements DFT solutions for large infrastructure ASICs, from RTL and test planning through tape-out, silicon bring-up, and manufacturing test.
What you'll do
- Define DFT architectures and flows, including scan, ATPG, memory test, and boundary scan.
- Generate and validate test patterns, analyze coverage, and complete DFT sign-off.
- Support manufacturing test and post-silicon debug, diagnosis, and yield improvement.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 6+ years of DFT engineering experience for complex ASIC or SoC designs, including scan insertion, ATPG pattern generation, and MBIST implementation.
- Experience with industry-standard DFT EDA tools and achieving high fault coverage across multiple fault models on multi-million gate designs.
- Experience supporting silicon bring-up and manufacturing test, and scripting in Tcl, Python, or Perl for DFT automation.
Nice to have
- Familiarity with IEEE 1500, IEEE 1687 (IJTAG), or IEEE 1149.1 boundary scan standards.
- Experience with high-speed SerDes, mixed-signal IP, or multi-die/chiplet DFT; at-speed test; or post-silicon failure analysis and yield improvement.
Pay
$146,000/year to $209,000/year USD base salary
Tools
Tessent, Synopsys DFT Compiler, TetraMAX, Tcl, Python, Perl, IEEE 1500, IEEE 1687 (IJTAG)
Model-written summary · the original posting is authoritative