ASIC Engineer, Design Verification

What you'll do

• Define verification plans and build testbenches for blocks, IP, subsystems, and SoCs; develop functional tests.
• Drive verification closure using test-plan metrics, functional coverage, and code coverage; debug and resolve design failures with Design teams.
• Collaborate with Design, Model, Emulation, and Silicon Validation teams to meet design-quality goals.

What they ask for

• 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++-based verification.
• 2+ years of block/IP/subsystem and/or SoC verification using SystemVerilog UVM/OVM methodologies.
• Experience with EDA tools and verification scripting, revision control systems, and developing UVM verification environments from scratch.
• Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience; degree must be completed before joining.

Nice to have

• Experience with high-speed interfaces such as PCIe, DDR, or Ethernet; ARM/RISC-V subsystems; or data-center designs such as Video, AI/ML, and Networking.
• Experience architecting verification infrastructure and executing the full verification cycle; track record of first-pass ASIC success.

Pay

USD $114,000/year to $172,000/year (base salary); bonus and equity are also stated, with no amounts specified.

Tools

SystemVerilog, UVM, C/C++, Python, TCL, Perl, Shell, Mercurial(Hg), Git or SVN

AI focus

Verification of data-center designs including Artificial Intelligence/Machine Learning (AI/ML).